A voltage-controlled oscillator (VCO) and a phase-locked loop (PLL) are commonly used components in many circuit designs. Jitter of the output clock signal in a VCO or a PLL determine the quality even the performance of the output signal. Therefore jitter measurement in a VCO and a PLL becomes indispensable in the field of circuit design.
As a result of the rapid advancement of VLSI technology, Frequently, a SoC (System on A Chip) has an embedded PLL. However, there are many restrictions posed when external measuring equipment measures a built-in PLL. Such restrictions include noise from measuring environment and package pins, bandwidth limitation of the external measuring equipment and lack of input and output interface for built-in PLL to external. Compare with prior art methods measuring by external equipment, an internal measuring circuit has advantages such as low cost, faster measuring, better precision, less restriction on measuring capacity, and ability to perform at-speed testing.
Jitter is often less than several hundred pico seconds in many cases. Conventionally, internal measurement technologies are usually implemented by analog designs, which are complicated and expensive.
LogicVision Inc. utilizes components including delay-lines for adjusting delays, flip-flops and counters for counting timing intervals, and then combining with statistics method for calculating jitter. Nonetheless, its precision and accuracy are limited to the resolution of the delay-lines and the setup time of the flip-flops.
Credence utilizes built-in clock generators for generating clocks of predefined periods. A signal to be measured is used for triggering the generated clocks. First cycle trigger the first generated clock and second cycle trigger the second generated clock. After the phase of the first generated clock matches the phase of the second generated clock, the period of the signal to be measured is determined by the number of cycles required for phase matching. By measuring the periods of the signal repeatedly, the jitter of the signal is determined combined with statistics method. The internal clock generators and matching decision devices used in such method restrict precision and accuracy of jitter measurement. Such method also requires extra device for performing statistics calculation and results in larger circuit area.
Precision level of jitter measurement taken by aforementioned methods only reaches several hundred pico seconds. Antonio H. Chan and Gordon W. Roberts proposed a paper titled “A Synthesizable, Fast and High-resolution Timing Measurement Device Using a Component-invariant Vernier Delay Line” in the International Test Conference, 2001. Chan and Roberts applied a differential method for overcoming the precision restriction caused by minimum delay of a component. However, the extra design cost grows exponentially with improved precision, also, the differential values of components will shift when implemented in different manufacturing process and result in undetermined precision and undesirable accuracy.